The present invention relates to a pull-up and a pull-down circuit, and particularly to those to be used for maintaining potential of certain nodes of an inner circuit of a semiconductor device at either of positive or negative power supply voltage level.
There are semiconductor devices whereof inner circuits are provided with pull-up or pull-down circuits for maintaining potential of certain nodes therein at positive or negative power supply voltage level. To a conventional pull-up circuit used in these semiconductor devices, a diode-connected nMOS (n-channel type Metal Oxide Semiconductor) transistor is applied, whereof gate being coupled with an end of current pass (drain or source, which is hereafter represented by drain), drain is connected to a positive power supply and source is connected to the node to be pulled up, while a diode connected pMOS (p-channel type MOS) transistor is applied to a conventional pull-down circuit, whereof source is connected to the node to be pulled down, drain coupled with its gate being connected to a negative power supply.
FIGS. 11A and 11B illustrate the above conventional pull-up and pull down circuit. The pull-up circuit of FIG. 11A comprises an nMOS transistor N1, whereof a gate is coupled with a drain and connected to a positive power supply Vcc, a source is connected to a pull-up node OU, and a substrate is connected to a ground GND.
Denoting threshold voltage counting the back-bias effect of the nMOS transistor N1 by Vtn, the maximum voltage of the pull-up node OU is expressed as Vcc--Vtn (Vcc being power supply voltage). Therefore, the pull-up node OU cannot be pulled up until to the power supply voltage Vcc. When the threshold voltage Vtn=1V and the power supply voltage Vcc=5V, the maximum voltage becomes (5-1)=4V, for example. Hence, the pull-up circuit of FIG. 11A is mainly used where the pull-up node needs lower voltage than the power supply voltage Vcc, or it cannot be connected but to an nMOS transistor.
Similarly, the pull-down circuit of FIG. 11B comprises a pMOS transistor P1, whereof a gate is coupled with a drain and connected to the ground GND, a source is connected to a pull-down node OD, and a substrate is biased by the positive power supply voltage Vcc.
Here also, the minimum voltage of the pull-down node OD is given by GND--Vtp (GND and Vtp being ground voltage and threshold voltage counting the back-bias effect of the pMOS transistor P1, respectively). Therefore, the pull-down node OD cannot be pulled down until to the ground voltage GND. When the threshold voltage Vtp=-1V and the ground voltage GND=0V, the minimum voltage becomes (0-(-1))=1V, for example. Hence, the pull-down circuit of FIG. 11B is mainly used where the pull-down node needs higher voltage than the ground voltage GND, or it cannot be connected but to a pMOS transistor.
Now, some examples of usage of these pull-up and pull-down circuits are described, in the following paragraphs.
FIG. 12 is a circuit diagram of a semiconductor circuit disclosed in a Japanese Patent published with a specification No. 50771/'95, comprising an input buffer 1 connected an input pad T1, an output buffer 3 connected to an output pad T2, and an inner logic circuit 2 connected between them. The input buffer 1 and the output buffer 3 are driven directly with a common power supply voltage Vcc for interfacing with outer circuits. On the other hand, the inner logic circuit 2 is driven with lower voltage supplied to a pull-up node OU from the positive power supply Vcc through pull-up circuits 4 having voltage regulation nMOS transistors N1. By lowering the driving voltage thus intentionally, application of short-channel high-speed transistors can be enabled in the inner logic circuit 2, with lower power consumption, as well.
FIGS. 13A and 13B are circuit diagrams illustrating charge-pump circuits disclosed in a Japanese patent application laid open as a Provisional Publication No. 103070/'96, wherein a pull-up circuit having an nMOS transistor N1 is used for supplying a first stage voltage to a first node NA1 of the charge-pump circuit of FIG. 13A for outputting a positive high voltage to an output terminal Vpcp, and similarly, a pull-down circuit having a pMOS transistor P1 is used for supplying a first stage voltage to a first node NB1 of the charge-pump circuit of FIG. 13B for outputting a negative high voltage to an output terminal Vncp.
The above pull-up and pull-down circuit operate normally when the power supply voltage Vcc or GND is well regulated. However, they have a problem that they may be easily broken when surges are impressed to the power supply voltage Vcc or GND, caused by static electricity, for example, resulting in failure of the semiconductor devices, as will be described in the following paragraphs.
FIG. 14A is a cross section schematically illustrating an example of a semiconductor configuration of the pull-up circuit of FIG. 11A having the nMOS transistor N1, wherein a gate electrode 104 is provided on an insulation film traversing n-type diffusion layers 102 and 103 configured on a p-type semiconductor substrate 100.
The n-type diffusion layers 102 and 103 compose the nMOS transistor N1 of the pull-up circuit (hereafter called the pull-up transistor) together with the gate electrode 104. The n-type diffusion layer 102 and the gate electrode 104 is connected to the positive power supply Vcc and another n-type diffusion layer 103 is connected to the pull-up node OU. Further, a p-type diffusion layer 105 is configured neighboring on the pull-up transistor N1 for supplying biasing voltage to the p-type semiconductor substrate 100. Elements of the pull-up transistor are separated from the p-type diffusion layer 105 with a field insulation film 101.
FIG. 14B is a cross section schematically illustrating another example of the semiconductor configuration comprising the pull-up circuit of FIG. 11A, wherein another nMOS transistor is composed of n-type diffusion layers 106 and 107 and a gate electrode 108 in place of the p-type diffusion layer 105 of FIG. 14A, neighboring the pull-up transistor N1 composed of the n-type diffusion layers 102 and 103 and the gate electrode 104. The pull-up transistor N1 and the other nMOS transistor are separated with the field insulation film 101 and the n-type diffusion layer 107 (source electrode of the other nMOS transistor) is connected to the ground GND.
FIG. 15 is a graphic chart illustrating voltage-current characteristics of current flowing from the n-type diffusion layer 102 to the ground GND through the p-type diffusion layer 105 of FIG. 14A or the n-type diffusion layer 107 of FIG. 14B, when a surge voltage higher than withstand voltage V1 is impressed to the n-type diffusion layer 102.
In the semiconductor configuration of FIG. 14A, a surge current Is represented by a curve L1 to L2 (passing a point AM) of FIG. 15 flows from the n-type diffusion layer 102 to the p-type diffusion layer 105 through the p-type semiconductor substrate 100, when a high voltage Vs higher than the withstand voltage V1 is impressed there because of a surge voltage V4 impressed to the positive power supply Vcc.
The n-type diffusion layer 102 being connected to the positive power supply Vcc through a low resistance metallic film, in general, the high voltage Vs at the n-type diffusion layer 102 drops little as represented by a curve L4 of FIG. 15, even when the surge current Is flows. Hence, the surge current Is increases up to a cross point (V3, I1) of the curves L2 and L4 as illustrated in FIG. 15. Thus, the n-type diffusion layer 102 is broken because of either of a high temperature caused by the surge current value I1 or an electric field caused by the high voltage of V3, when one of them is too high.
In case of the semiconductor configuration of FIG. 14B, the surge current Is flows following the curve L1 in the same way with the case of FIG. 14A, when the high-voltage Vs higher than the withstand voltage V1 is impressed. The surge current Is flows injecting positive holes into the p-type semiconductor substrate 100, and potential of the p-type semiconductor substrate 100 is made higher. Therefore, when the surge current Is arrives to 12 at the point AM of FIG. 15, for example, the p-n junction between the neighboring n-type diffusion layer 107, which is grounded, and the p-type semiconductor substrate 100 becomes forward biased and electrons begin to be injected from the n-type diffusion layer 107 for the n-type diffusion layer 102, giving a negative resistance characteristic between them, as represented by a curve L3 beginning from the point AM of FIG. 15.
Therefore, the n-type diffusion layer 102 may be broken in the case of the semiconductor configuration of FIG. 14B because of the high temperature caused by the intense surge current Is following the curve L3 triggered by lower surge voltage V2.
These breakdowns of the pull-up transistor N1 come mainly from the fact that the positive power supply Vcc is directly connected by the low resistance metallic film to the n-type diffusion layer 102 configured on the p-type semiconductor substrate 100 which is, however, biased to the ground voltage GND commonly with other circuit elements.
For preventing these breakdowns of the n-type diffusion layer, various considerations are paid until now for designing element layout of the pull-up transistor to be configured on a semiconductor device, in order to improve withstand voltage thereof by lightening electric field intensity or reserving necessary distance for reducing the surge current intensity.
FIG. 16 is a schematic diagram illustrating an example of element layout of a conventional pull-up transistor comprising a gate electrode 202 and an n-type diffusion layer 201, drain side thereof being coupled by contact points (one of them being denoted by a numeral 205) with a metallic wiring film 204 supplied with the power supply voltage Vcc and source side thereof coupled by contact points with another metallic wiring film 203 connecting to the output node OU.
In general, the breakdown of the n-type diffusion layer because of high voltage begins at an edge part thereof or a part thereof connecting to the gate edge. Therefore, distance D1 from the contact point (205, for example) to the edge of the n-type diffusion layer 201 and that D2 to the edge of the gate electrode 202 are made longer for the pull-up transistor, expecting current suppression by the diffusion layer resistance, compared to corresponding distances D11 and D12 of other ordinary transistors, composed of a gate electrode 211 and an n-type diffusion layer 210, for example, in the prior art of FIG. 16.
As for also the gate electrode 202, a long wiring path is provided between a channel part and a contact point supplied with the positive power supply Vcc of the gate electrode 202, expecting a long time constant given by resistance and capacitance thereof to prevent a high-peak trigger which may cause an insulation film breakdown between the gate electrode 202 and the substrate or the source side of the n-type diffusion layer 201.
Furthermore, for preventing the intense surge current because of the negative resistance as described in connection with FIG. 14B, a p-type diffusion layer 206 connected to the ground GND is provided in the element layout of FIG. 16 for separating the pull-up transistor and the n-type diffusion layer 210, for example, of other ordinary nMOS transistors connected to the ground GND, so that the n-type diffusion layer 210 may not be forward biased to the substrate potential thereabout made high.
In addition, distances between the pull-up transistor and the p-type diffusion layer 206 and the n-type diffusion layer 210 are made longer than ordinary layout arrangement in order to increase withstand voltage of the pull-up transistor, in the element layout of FIG. 16.
These are representative examples of layout consideration for improving withstand voltage of the pull-up transistor.
However, these layout techniques need a larger space of the semiconductor chips inevitably, resulting in low productivity and high production cost thereof.
Further, the element layout, or the size arrangement, is very difficult because it must be designed considering various factors such as growth methods of diffusion layers or resistance values of substrate materials. So, the withstand voltage performance of semiconductor devices cannot be estimated in many cases until they are tested after fabrication, and the element layout should be re-designed again when it is found to be insufficient.
Heretofore, problems of the pull-up transistor are described. However, the pull-down transistor has the same problems except for polarity difference, wherein the p-type diffusion layer is broken when a negative high voltage is impressed to the p-type diffusion layer connected directly to the ground GND relative to the substrate potential of the pMOS pull-down transistor biased to the positive power supply voltage Vcc.